1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming photoresist patterns having a reduced height.
2. Description of the Related Art
The speed of logic devices and central processing (“CPU”) devices increases with a reduction in the size of gates. In particular, the space between gates becomes narrower in a cell having reduced gate sizes and a narrow pitch. Such devices may have an increased likelihood of “punch-through” by hot carriers. A nonuniformly-doped area may result in a decrease in the likelihood of punch-through by hot carriers in such devices. Nonuniform-doping may be performed with the implantation of ions.
Hereinafter, a general method of forming photoresist patterns for the implantation of ions will be described with reference to the attached drawings.
FIGS. 1 and 2 are schematic drawing for illustrating a method of forming photoresist patterns for the implantation of ions. Referring to FIG. 1, a semiconductor substrate 10 is coated with photoresist to form a photoresist layer 12. A mask pattern 11 includes transparent patterns 14 having a light transmissivity of about 100% and non-transparent patterns 16 having a light transmissivity of about 0%. The non-transparent patterns 16 may be formed of a non-transparent material such as chrome (Cr). Light passing through the mask pattern exposes selected areas of the photoresist 12.
Referring to FIG. 2, the photoresist layer 12 (FIG. 1) is exposed and developed to form photoresist patterns 18 such that ions may be implanted in the semiconductor substrate 10 at a doping angle θ. The “doping angle θ” refers to the angle at which ions are implanted on the substrate 10. Developing photoresist layer 12 using mask pattern 11 (FIG. 1) results in void areas 17 and photoresist pattern 18. The mask pattern 11 shields portions of the photoresist layer 12 and exposes other areas of the photoresist layer 12.
Materials for forming a photoresist layer 12 (FIG. 1) generally have relatively high etch resistance. That is, the photoresist patterns 18 which result from unexposed areas in the photoresist layer 12 are virtually unaffected by the exposure and etching of surrounding void area 17. In addition, conventional methods and materials used to form, expose, and develop a photoresist layer 12 and the photoresist layer 12 limit the resulting thickness of the photoresist layer 12. More specifically, the thickness of the photoresist layer 12 is generally equal to or greater than about 7,400 Å. Because of the high etch resistance of conventional photoresist materials, the height of the photoresist patterns 18 is almost identical to the thickness of the photoresist layer 12 (FIG. 1). High etching resistance is generally desirable to maintain the photoresist pattern 18.
In one application of photoresist patterns 18, the photoresist patterns 18 may function as a mask on the substrate 10 to perform ion implantation 20. The photoresist pattern 18 may be used to nonuniformly dope the semiconductor substrate 10 with ions. As shown in FIG. 2, the ion implantation 20 is performed at an angle of between about 60° and about −60°, with respect to the normal of the semiconductor substrate 10, to nonuniformly dope the semiconductor substrate 10 with ions.
In certain applications, gates may be fabricated on the semiconductor substrate 10, for example, in an area on the surface of the substrate 10 covered by the photoresist pattern 18. Because of improvements in semiconductor fabrication techniques, it is possible to reduce the size of the gates and the spaces between the gates. As a result, the void area 17 between photoresist pattern 18 is reduced and the aspect ratio of the photoresist patterns 18 is increased. If the height of the photoresist pattern 18 remains the same, it becomes difficult to achieve an appropriate doping angle θ due to the resulting geometries of a relatively high photoresist pattern 18 and relatively narrow void area 17. It is preferable that the height of photoresist patterns 18 is within 3,000-6,000 Å, which is almost identical to the height of gates, to achieve the appropriate doping angle θ. However, the thickness of the photoresist layer 12 formed through conventional methods and materials is typically about 7,400 Å.
One potential solution is to form a thinner photoresist layer 12 to achieve the appropriate doping angle θ geometry. However, if the photoresist layer 12 is thin, the step difference between the gates may stand out. Attempts to form such a photoresist layer may result in insufficient quality and characteristics in photoresist layer 12. In particular, a deep ultra-violet (DUV) process must be performed to form fine patterns. The poor coating of photoresist layer 12 may also cause nonuniformity in a critical dimension. As a result, it is difficult to perform an appropriate photolithography process with a relatively thin photoresist layer 12, for example, a photoresist layer 12 that is thinner than about 7,400 Å.